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mips PR31500 poseidon embedded processor preliminary specification 1996 sep 24 integrated circuits version 0.1
philips semiconductors preliminary specification mips PR31500 poseidon embedded processor version 0.1 2 1996 sep 24 general description PR31500 processor is a single-chip, low-cost, integrated embedded processor consisting of mips r3000 core and system support logic to interface with various types of devices. PR31500 consists of a mips r3000 risc cpu with 4 kbytes of instruction cache memory and 1 kbyte of data cache memory , plus integrated functions for interfacing to numerous system components and external i/o modules. the r3000 risc cpu is also augmented with a multiply/accumulate module to allow integrated dsp functions, such as a software modem for high-performance standard data and fax protocols. the PR31500 processor can support both little and big endian operating systems. in addition the PR31500 provides a memory management unit with an on-chip t ranslation look aside buffer (tlb) for very fast virtual to physical address translation. PR31500 also contains multiple dma channels and a high-performance and flexible bus interface unit (biu) for providing an ef ficient means for transferring data between external system memory, cache memory , the cpu core, and external i/o modules. the types of external memory devices supported include dynamic random access memory (dram), synchronous dynamic random access memory (sdram), static random access memory (sram), flash memory , read-only memory (rom), and expansion cards (e.g., pcmcia). PR31500 also contains a system interface module (sim) containing integrated functions for interfacing to numerous external i/o modules such as liquid crystal displays (lcds), the ucb1 100 (which handles most of the analog functions of the system, including sound and telecom codecs and touchscreen adc), isdn/high-speed serial, infrared, wireless peripherals, etc. lastly , PR31500 contains support for implementation of power management, whereby various PR31500 internal modules and external subsystems can be individually (under software control) powered up and down. figure 1 shows an external block diagram of PR31500. features ? 32-bit r3000 risc static cmos cpu ? 4 kbyte instruction cache ? 1 kbyte data cache ? multiply/accumulator instruction ? r3000a memory management unit with on-chip tlb ? supports big/little endian operating systems ? on-chip peripherals with individual power-down multi-channel dma controller bus interface unit memory controller for rom, flash, ram, dram, sdram, sram, and pcmcia power management module video module real-time clock 32.760khz reference high-speed serial interface infrared module dual-uart spi bus ? 3.3v supply voltage ? 208-pin lqfp (low profile quad flat pack) ? 40mhz operation frequency ordering information part number temperature range ( c) and package frequency (mhz) drawing number PR31500abc 0 to +70, 208-pin low profile quad flat pack 40 lqfp208
philips semiconductors preliminary specification mips PR31500 poseidon embedded processor 1996 sep 24 3 ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? r3000 risc cpu core icache 4kbyte dcache 1kbyte bus interface unit (biu) module (s)dram/pcmcia/rom data addr chi module addr data data addr control to ucb1100 to lcd to high speed serial to ir timer module (+ rtc) ir module uart module (dual uart) mac to uart power module spi module to power supply io module to general purpose i/o 32 khz sysclk interrupt module system interface module (sim) to memory cpu module data tag addr system interface unit (siu) module arbitration/dma/addrdecode video module sib module mmu clock module sn00162 figure 1. PR31500 block diagram
philips semiconductors preliminary specification mips PR31500 poseidon embedded processor 1996 sep 24 4 overview each of the on-chip peripherals consist of: biu module ? system memory and PR31500 bus interface unit (biu) supports up to 2 banks of physical memory supports self-refreshing dram and sdram programmable parameters for each bank of dram or sdram (row/column address configuration, refresh, burst modes, etc.) ? programmable chip select memory access 4 programmable (size, wait states, burst mode control) memory device and general purpose chip selects available for system rom, sram, flash available for external port expansion registers ? supports up to 2 identical full pcmcia ports PR31500 and ucb1 100 provide the control signals and accepts the status signals which conform to the pcmcia version 2.01 standard appropriate connector keying and level-shifting buf fers required for 3.3v versus 5v pcmcia interface implementations siu module ? multi-channel 32-bit dma controller and system interface unit (siu) ? independent dma channels for video, sib to/from ucb1 100 audio/telecom codecs, high-speed serial port, ir uar t, and general purpose uart ? address decoding for submodules within system interface module (sim) cpu module ? r3000 risc central processing unit core full 32-bit operation (registers, instructions, addresses) 32 general purpose 32-bit registers; 32-bit program counter mips risc instruction set architecture (isa) supported ? on-chip cache 4 kbyte direct-mapped instruction cache (i-cache) physical address tag and valid bit per cache line programmable burst size instruction streaming mode supported 1 kbyte data cache (d-cache) physical address tag and valid bit per cache line programmable burst size write-through cache address snoop mode supported for dma 4-level deep write buffer ? memory management unit mips r3000a mmu contains on-chip tlb with: 32 64 bit wide entries fully associative 2 entry micro tlb for very fast instruction address translation instruction address translation accesses full tlb after micro tlb miss data address translation accesses full tlb ? high-speed multiplier/accumulator on-chip hardware multiplier supports 16x16 or 32x32 multiplier operations, with 64-bit accumulator existing multiply instructions are enhanced and new multiply and add instructions are added to r3000 instruction set to improve the performance of dsp applications ? cpu interface handles data bus, address bus, and control interface between cpu core and rest of PR31500 logic clock module ? PR31500 supports system-wide single crystal configuration, besides the 32 khz rtc xtal (reduces cost, power, and board space) ? common crystal rate divided to generate clock for cpu, video, sound, telecom, uarts, etc. ? external system crystal rate is vendor-dependent ? independent enabling or disabling of individual clocks under software control, for power management chi module ? high-speed serial concentration highway interface (chi) contains logic for interfacing to external full-duplex serial time-division-multiplexed (tdm) communication peripherals ? supports isdn line interface chips and other pcm/tdm serial devices ? chi interface is programmable (number of channels, frame rate, bit rate, etc.) to provide support for a variety of formats ? supports data rates up to 4.096 mbps ? independent dma support for chi receive and transmit interrupt module ? contains logic for individually enabling, reading, and clearing all PR31500 interrupt sources ? interrupts generated from internal PR31500 modules or from edge transitions on external signal pins io module ? contains support for reading and writing the 7 bi-directional general purpose io pins and the 32 bi-directional multi-function io pins ? each io port can generate a separate positive and negative edge interrupt ? independently configurable io ports allow PR31500 to support a flexible and wide range of system applications and configurations
philips semiconductors preliminary specification mips PR31500 poseidon embedded processor 1996 sep 24 5 ir module ? ir consumer mode allows control of consumer electronic devices such as stereos, tvs, vcrs, etc. programmable pulse parameters external analog led circuitry ? irda communication mode allows communication with other irda devices such as f ax machines, copiers, printers, etc. supported by uart module within PR31500 external analog receiver preamp and led circuitry data rate = up to 115 kbps at 1 meter ? ir fsk communication mode supported by uart module within PR31500 external analog ir chip(s) perform frequency modulation to generate the desired ir communication mode protocol data rate = up to 36000 bps at 3 meters ? carrier detect state machine periodically enables ir receiver to check if a valid carrier is present power module ? power-down modes for individual internal peripheral modules ? serial (spi port) power supply control interface supported ? power management state machine has 4 states: running, dozing, sleep, and coma serial interconnect bus (sib) module ? PR31500 contains holding and shift registers to support the serial interface to the ucb1 100 and/or other optional codec devices ? interface compatible with slave mode 3 of crystal cs4216 codec ? synchronous, frame-based protocol ? PR31500 always master source of clock and frame frequency and phase; programmable clock frequency ? each sib frame consists of 128 clock cycles, further divided into 2 subframes or words of 64 bits each (supports up to 2 devices simultaneously) ? independent dma support for audio receive and transmit, telecom receive and transmit ? supports 8-bit or 16-bit mono telecom formats ? supports 8-bit or 16-bit mono or stereo audio formats ? independently programmable audio and telecom sample rates ? cpu read/write registers for subframe control and status system peripheral interface (spi) module ? provides interface to spi peripherals and devices ? full-duplex, synchronous serial data transfers (data in, data out, and clock signals) ? PR31500 supplies dedicated chip select and interrupt for an spi interface serial power supply ? 8-bit or 16-bit data word lengths for the spi interface ? programmable spi baud rate timer module ? real time clock (rtc) and timer ? 40-bit counter (30.517 m sec granularity); maximum uninterrupted time = 388.36 days ? 40-bit alarm register (30.517 m sec granularity) ? 16-bit periodic timer (0.868 m sec granularity); maximum timeout = 56.8 msec ? interrupts on alarm, timer, and prior to rtc roll-over uart module ? 2 independent full-duplex uarts ? programmable baud rate generator ? uart -a port used for serial control interface to external ir module ? uart -b port used for general purpose serial control interface ? uart-a and uart-b dma support for receive and transmit video module ? bit-mapped graphics ? supports monochrome, grey scale, or color modes ? time-based dithering algorithm for grey scale and color modes ? supports multiple screen sizes ? supports split and non-split displays ? variable size and relocatable video buf fer ? dma support for fetching image data from video buf fer little/big endian configuration the PR31500 can be configures as a big endian or as a little endian processor based on the /lb endian pin at power-up. the byte ordering is as follows: little endian big endian d[31:24] d[7:0] d[23:16] d[15:8] d[15:8] d[23:16] d[7:0] d[31:24] /cas3 /cas0 /cas2 /cas1 /cas1 /cas2 /cas0 /cas3
philips semiconductors preliminary specification mips PR31500 poseidon embedded processor 1996 sep 24 6 figure 2 shows a typical system block diagram cosisting of PR31500 and ucb1100 for a total system solution. r3000 risc cpu core icache/ram dcache/ ram 32bit bus lcd interface timers realtime clock serial i/f and magicbus 12 pcmcia slots ucb1100 main backup (lithium) daa rf xceiver or touchscreen (resistive) phone jack ir PR31500 ac adapter 3.3v memory protection pcmcia/rom i/f 164 mbytes rom 116 mbytes (s)dram ?? ?? ?? ?? t thermistor 3.3v 32 khz sysclk ??? ??? ??? ??? id rom ??? ??? ??? ??? high speed serial port isdn or other peripherals lcd dram/sdram interface power supply tlb sn00163 figure 2. system block diagram
philips semiconductors preliminary specification mips PR31500 poseidon embedded processor 1996 sep 24 7 pin configuration 208 1 52 53 104 105 156 157 208-pin plastic quad flat pack top view pin function 1 v dd 2 d(0) [d(24)] 3 v ss 4 d(1) [d(25)] 5 d(2) [d(26)] 6 v dd 7 d(3) [d(27)] 8 v ss 9 d(4) [d(28)] 10 v dd 11 d(5) [d(29)] 12 d(6) [d(30)] 13 v ss 14 d(7) [d(31)] 15 v ss 16 d(8) [d(16)] 17 v dd 18 d(9) [d(17)] 19 d(10) [d(18)] 20 v ss 21 d(11) [d(19)] 22 v dd 23 d(12) [d(20)] 24 d(13) [d(21)] 25 v ss 26 d(14) [d(22)] 27 d(15) [d(23)] 28 v dd 29 /lb endian 30 mfio(1) 31 32 33 v ss 34 35 v dd 36 v dd 37 sibmclk 38 v ss 39 sibsclk 40 sibsync 41 sibdin 42 sibdout 43 v dd 44 sibirq 45 mfio(0) 46 io(6) 47 io(50 48 v ss 49 chiclk 50 chifs 51 chidin 52 chidout pin function 53 v dd 54 rxd 55 txd 56 io(4) 57 58 irin 59 irout 60 v ss 61 v dd 62 cardet 63 txpwr 64 io(3) 65 io(2) 66 v ss 67 spiclk 68 spiin 69 spiout 70 v dd 71 testcpu 72 testin 73 viddone 74 testsiu 75 v ss 76 v cc 3 77 bc32k 78 v dd 79 c32kin 80 c32kout 81 v ss 82 pwrcs 83 pwrint 84 pwrok 85 86 onbutn 87 /pon 88 /cpures 89 v dd 90 dispon 91 frame 92 v ss 93 df 94 load 95 cp 96 v ss 97 v dd 98 vdat(0) 99 vdat(1) 100 vdat(2) 101 vdat(3) 102 v ss 103 io(1) 104 v dd pin function 105 /card2wait 106 /card2csh 107 /card2csl 108 io(0) 109 v ss 110 /iord 111 /iowr 112 /cardreg 113 /card1wait 114 v dd 115 mfio(2) 116 v dd 117 /card1csl 118 /card1csh 119 v ss 120 /mcs3 121 /mcs2 122 /mcs1 123 /mcs0 124 /cs3 125 /cs2 126 /cs1 127 v dd 128 sysclkin 129 sysclkout 130 v ss 131 v ss 132 v dd 133 d(31) [d(7)] 134 d(30) [d(6)] 135 v ss 136 d(29) [d(5)] 137 v dd 138 d(28) [d(4)] 139 d(27) [d(3)] 140 v ss 141 d(26) [d(2)] 142 v ss 143 d(25) [d(1)] 144 v dd 145 d(24) [d(0)] 146 d(23) [d(15)] 147 v dd 148 d(22) [d(14)] 149 v ss 150 d(21) [d(13)] 151 v dd 152 d(20) [d(12)] 153 d(19) [d(11)] 154 v ss 155 d(18) [d(10)] 156 v dd pin function 157 d(17) [d(9)] 158 v ss 159 d(16) [d(8)] 160 v dd 161 162 /cs0 163 /rd 164 v ss 165 v dd 166 /dgrnt 167 /dreq 168 ale 169 /we 170 v dd 171 a(12) 172 a(11) 173 v ss 174 a(10) 175 a(9) 176 v dd 177 a(8) 178 a(7) 179 v ss 180 a(6) 181 a(5) 182 v dd 183 a(4) 184 v ss 185 a(3) 186 a(2) 187 v dd 188 a(1) 189 a(0) 190 v ss 191 v ss 192 /dcs0 193 /ras1 194 /ras0 195 /cas3 [/cas0] 196 v dd 197 /cas2 [/cas1] 198 /cas1 [/cas2] 199 /cas0 [/cas3] 200 v ss 201 v dd 202 dcke 203 v ss 204 dclkin 205 dclkout 206 v dd 207 dqmh 208 dqml note: [ ] indicates the signal name in the little endian mode. sn00164
philips semiconductors preliminary specification mips PR31500 poseidon embedded processor 1996 sep 24 8 pin descriptions overview the PR31500 processor contains 208 pins consisting of input, output, bi-directional, and power and ground pins. these pins are used to support various functions. the following sections will describe the function of each pin including any special power-down considerations for each pin. pins the PR31500 processor contains 208 total pins, consisting of 136 signal pins, 4 spare pins, 34 power pins, and 34 ground pins. of the 136 signal pins, 32 of them are multi-function and can be independently programmed either as io ports or for an alternate standard/normal function. as an io port, any of these pins can be programmed as an input or output port, with the capability of generating a separate positive and negative edge interrupt. see section 2.3 for a summary of the multi-function io ports versus their standard functions. pin # name type name and function memory pins d(31:0) i/o these pins are the data bus for the system. 8-bit sdrams should be connected to bits 7:0 and 16-bit sdrams and drams should be connected to bits 15:0. all other 16-bit ports should be connected to bits 31:16. of course, 32-bit ports should be connected to bits 31:0. these pins are normally outputs and only become inputs during reads, thus no resistors are required since the bus will only float for a short period of time during bus turn-around. a(12:0) o these pins are the address bus for the system. the address lines are multiplexed and can be connected directly to sdram and dram devices. t o generate the full 26-bit address for static devices, an external latch must be used to latch the signals using the ale signal. for static devices, address bits 25:13 are provided by the external latch and address bits 12:0 (directly connected from PR31500' s address bus) are held afterward by PR31500 processor for the remainder of the address bus cycle. 168 ale o this pin is used as the address latch enable to latch a(12:0) using an external latch, for generating the upper address bits 25:13. 163 /rd o this pin is used as the read signal for static devices. this signal is asserted for reads from /mcs3-0, /cs3-0, /card2cs and /card1cs for memory and attribute space, and for reads from PR31500 processor accesses if showPR31500 is enabled (for debugging purposes). 169 /we o this pin is used as the write signal for the system. this signal is asserted for writes to /mcs3-0, /cs3-0, /card2cs and /card1cs for memory and attribute space, and for writes to dram and sdram. 199 /cas0 (/we0) o this pin is used as the cas signal for sdrams, the cas signal for d(7:0) for drams, and the write enable signal for d(7:0) for static devices. 198 /cas1 (/we1) o this pin is used as the cas signal for d(15:8) for drams and the write enable signal for d(15:8) for static devices. 197 /cas2 (/we2) o this pin is used as the cas signal for d(23:16) for drams and the write enable signal for d(23:16) for static devices. 195 /cas3 (/we3) o this pin is used as the cas signal for d(31:24) for drams and the write enable signal for d(31:24) for static devices. 194 /ras0 o this pin is used as the ras signal for sdrams and the ras signal for bank0 drams. 193 /ras1 (/dcs1) o this pin is used as the chip select signal for bank1 sdrams and the ras signal for bank1 drams. 192 /dcs0 o this pin is used as the chip select signal for bank0 sdrams. 202 dcke o this pin is used as the clock enable for sdrams. 204 dclkin i this pin must be tied externally to the dclkout signal and is used to match skew for the data input when reading from sdram and dram devices. 205 dclkout o this pin is the (nominal) 73.728 mhz clock for the sdrams. 207 dqmh o this pin is the upper data mask for a 16-bit sdram configuration. 208 dqml o this pin is the lower data mask for a 16-bit sdram or 8-bit sdram configuration. 124126, 162 /cs30 o these pins are the chip select 3 through 0 signals. they can be configured to support either 32-bit or 16-bit ports. 120123 /mcs30 o these pins are the magiccard chip select 3 through 0 signals. they only support 16-bit ports. 106, 107 /card2csh,l o these pins are the chip select signals for pcmcia card slot 2.
philips semiconductors preliminary specification mips PR31500 poseidon embedded processor 1996 sep 24 9 pin # name and function type name memory pins (continued) 117, 118 /card1csh,l o these pins are the chip select signals for pcmcia card slot 1. 112 /cardreg o this pin is the /reg signal for the pcmcia cards. 110 /cardiord o this pin is the /iord signal for the pcmcia io cards. 111 /cardiowr o this pin is the /iowr signal for the pcmcia io cards. 115 /carddir o this pin is used to provide the direction control for bi-directional data buf fers used for the pcmcia slot(s). this signal will assert whenever /card2csh or /card2csl or /card1csh or /card1csl is asserted and a read transaction is taking place. 105 /card2wait i this pin is the card wait signal from pcmcia card slot 2. 113 /card1wait i this pin is the card wait signal from pcmcia card slot 1. bus arbitration pins 167 /dreq i this pin is used to request external arbitration. if the testsiu signal is high and the testsiu function has been enabled, then once /dgrnt is asserted, external logic can initiate reads or writes to PR31500 processor registers by driving the appropriate input signals. if the testsiu signal is low or the testsiu function has not been enabled, then PR31500 memory transactions are halted and certain memory signals will be tri-stated when /dgrnt is asserted in order to allow an external master to access memory. 166 /dgrnt o this pin is asserted in response to /dreq to inform the external test logic or bus master that it can now begin to drive signals. clock pins 128 sysclkin i this pin should be connected along with sysclkout to an external crystal which is the main PR31500 clock source. 129 sysclkout o this pin should be connected along with sysclkin to an external crystal which is the main PR31500 clock source. 79 c32kin i this pin along with c32kout should be connected to a 32.768 khz crystal. 80 c32kout o this pin along with c32kin should be connected to a 32.768 khz crystal. 77 bc32k o this pin is a buf fered output of the 32.768 khz clock. chi pins 50 chifs i/o this pin is the chi frame synchronization signal. this pin is available for use in one of two modes. as an output, this pin allows PR31500 to be the master chi sync source. as an input, this pin allows an external peripheral to be the master chi sync source and the PR31500 chi module will slave to this external sync. 49 chiclk i/o this pin is the chi clock signal. this pin is available for use in one of two modes. as an output, this pin allows PR31500 to be the master chi clock source. as an input, this pin allows an external peripheral to be the master chi clock source and the PR31500 chi module will slave to this external clock. 52 chidout o this pin is the chi serial data output signal. 51 chidin i this pin is the chi serial data input signal. io pins 46, 107, 47, 108, 56, 64, 64 io(6:0) i/o these pins are general purpose input/output ports. each port can be independently programmed as an input or output port. each port can generate a separate positive and negative edge interrupt. each port can also be independently programmed to use a 16 to 24 msec debouncer . 30, 45 mfio(1:0) i/o these pins are multi-function input/output ports. each port can be independently programmed as an input or output port, or can be programmed for multi-function use to support vendor-dependent test signals (for debugging purposes only). each port can generate a separate positive and negative edge interrupt. note that 30 other multi-function pins are available for usage as multi-function input/output ports. these pins are named after their respective standard/normal function and are not listed here. endian processor pin 29 /lb endian i little/big endian. this pin, when pulled low at power-up, configures the PR31500 as a little endian. when this pin is pulled high at power-up, it configures the PR31500 as a big endian processor.
philips semiconductors preliminary specification mips PR31500 poseidon embedded processor 1996 sep 24 10 pin # name and function type name reset pins 88 /cpures i this pin is used to reset the cpu core. this pin should be connected to a switch for initiating a reset in the event that a software problem might hang the cpu core. the pin should also be pulled up to vst andby through an external pull-up resistor . 87 /pon i this pin serves as the power on reset signal for PR31500. this signal must remain low when vstandby is asserted until vstandby is stable. once vstandby is asserted, this signal should never go low unless all power is lost in the system. power supply pins 86 onbutn i this pin is used as the on button for the system. asserting this signal will cause pwrcs to set to indicate to the system power supply to turn power on to the system. pwrcs will not assert if the pwrok signal is low. 82 pwrcs o this pin is used as the chip select for the system power supply . when the system is off, the assertion of this signal will cause the system power supply to turn vccdram and vcc3 on to power up the system. the power supply will latch spi commands on the falling edge of pwrcs. 84 pwrok i this pin provides a status from the system power supply that there is a good source of power in the system. this signal typically will be asserted if there is a battery charger supplying current or if the main battery is good and the battery door is closed. if pwrok is low when the system is powered of f, pwrcs will not assert as a result of the user pressing the onbutn or an interrupt attempting to wake up the system. if the device is on when the pwrok signal goes low , the software will immediately shut down the system since power is about to be lost. when pwrok goes low , there must be ample warning so that the software can shut down the system before power is actually lost. 83 pwrint i this pin is used by the system power supply to alert the software that some status has changed in the system power supply and the software should read the status from the system power supply to find out what has changed. these will be low priority events, unlike the pwrok status, which is a high priority emergency case. 76 vcc3 i this pin provides the status of the power supply for the rom, ucb1 100, system buffers, and other transient components in the system. this signal will be asserted by the system power supply when pwrcs is asserted, and will always be turned of f when the system is powered down. sib pins 41 sibdin i this pin contains the input data shifted from ucb1 100 and/or external codec device. 42 sibdout o this pin contains the output data shifted to ucb1 100 and/or external codec device. 39 sibsclk o this pin is the serial clock sent to ucb1 100 and/or external codec device. the programmable sibsclk rate is derived by dividing down from sibmclk. 40 sibsync o this pin is the frame synchronization signal sent to ucb1 100 and/or external codec device. this frame sync is asserted for one clock cycle immediately before each frame starts and all devices connected to the sib monitor sibsync to determine when they should transmit or receive data. 44 sibirq i this pin is a general purpose input port used for the sib interrupt source from ucb1 100. this interrupt source can be configured to generate an interrupt on either a positive and/or negative edge. 37 sibmclk i/o this pin is the master clock source for the sib logic. this pin is available for use in one of two modes. first, sibmclk can be configured as a high-rate output master clock source required by certain external codec devices. in this mode all sib clocks are synchronously slaved to the main PR31500 system clock clk2x. conversely , sibmclk can be configured as an input slave clock source. in this mode, all sib clocks are derived from an external sibmclk oscillator source, which is asynchronous with respect to clk2x. also, for this mode, sibmclk can still be optionally used as a high-rate master clock source required by certain external codec devices. spi pins 67 spiclk o this pin is used to clock data in and out of the spi slave device. 69 spiout o this pin contains the data that is shifted into the spi slave device. 68 spiin i this pin contains the data that is shifted out of the spi slave device.
philips semiconductors preliminary specification mips PR31500 poseidon embedded processor 1996 sep 24 11 pin # name and function type name uart and ir pins 55 txd o this pin is the uart transmit signal from the uarta module. 54 rxd i this pin is the uart receive signal to the uarta module. 59 irout o this pin is the uart transmit signal from the uar tb module or the consumer ir output signal if consumer ir mode is enabled. 58 irin i this pin is the uart receive signal to the uartb module. rxpwr o this pin is the receiver power output control signal to the external communication ir analog circuitry. 62 cardet i this pin is the carrier detect input signal from the external communication ir analog circuitry . video pins 91 frame o this pin is the frame synchronization pulse signal between the v ideo module and the lcd, and is used by the lcd to return it' s pointers to the top of the display . the video module asserts frame after all the lines of the lcd have been shifted and transferred, producing a full frame of display . 93 df o this pin is the ac signal for the lcd. since lcd plasma tends to deteriorate whenever subjected to a dc voltage, the df signal is used by the lcd to alternate the polarity of the row and column voltages used to turn the pixels on and of f. the df signal can be configured to toggle on every frame or can be configured to toggle every programmable number of load signals. 94 load o this pin is the line synchronization pulse signal between the v ideo module and the lcd, and is used by the lcd to transfer the contents of it' s horizontal line shift register to the lcd panel for display. the v ideo module asserts load after an entire horizontal line of data has been shifted into the lcd. 95 cp o this pin is the clock signal for the lcd. data is pushed by the v ideo module on the rising edge of cp and sampled by the lcd on the falling edge of cp . 101, 100, 99, 98 vdat(3:0) o these pins are the data for the lcd. these signals are directly connected to the lcd for 4-bit non-split displays. for 4-bit split and 8-bit non-split displays, an external register is required to demultiplex the 4-bit data into the desired 8 parallel data lines needed for the lcd. 90 dispon o this pin is the display-on enable signal for the lcd. test pins 74 testsiu i this pin allows external logic to initiate read or write transactions to PR31500 registers. the testsiu mode is enabled by toggling this signal after the device has powered up. once the function is enabled, if the testsiu pin is high when the bus is arbitrated (using /dreq and /dgrnt), then external logic can initiate read and write transactions to PR31500 registers. this pin is used for debugging purposes only . 71 testcpu i this pin allows numerous internal cpu core signals to be brought to external PR31500 pins, in place of the normal signals assigned to these pins. the cpu core signals assigned to their respective pins during testcpu mode are vendor-dependent. the testcpu mode is enabled by asserting this testcpu signal, and this function is provided for generating test vectors for the cpu core. this pin is used for debugging purposes only . 72 testin i this pin is reserved for vendor-dependent use. this pin is used for debugging purposes only . 73 viddone o this signal is used to synchronize ucb1 100 to read touchscreen input, when there is no video data shifted into lcd panel. spare pins nc41 no connect these pins are reserved for future use and should be left unconnected. 34 reserved. 32, 31 reserved. power supply pins v dd (34 each) +3.3v these pins are the power pins for PR31500 and should be connected to the digital +3.3v power supply vstandby. v ss (34 each) gnd these pins are the ground pins for PR31500 and should be connected to digital ground. note: for some vendor-dependent implementations of PR31500, pin 131 may be used for a filter capacitor for the sysclk oscillator (capacitor connected between pin 131 and digital ground).
philips semiconductors preliminary specification mips PR31500 poseidon embedded processor 1996 sep 24 12 electrical characteristics absolute maximum ratings v ss = 0v symbol parameter limits unit v dd power supply voltage v ss 0.5 to 4.5 v v in input voltage v ss 0.5 to v dd + 0.5 v t stg storage temperature range 55 to +125 c pd maximum dissipation (t amb = 70 c) 1 w recommended operating condition v ss = 0v symbol parameter limits unit symbol parameter min typ max unit v dd power supply voltage 3.0 3.3 3.6 v v in input voltage v ss v dd v t opr operating temperature range 0 70 c dc electrical characteristics t amb = 0 to +70 c, v dd = 3.3 0.3v. symbol parameter conditions limits unit symbol parameter conditions min typ max unit i dd operating current v in = v dd or v ss ; v dd = max i oh = i ol = 0 110 tbd ma i dds static current v in = v dd or v ss ; v dd = max i oh = i ol = 0 10 100 m a i l input leakage current v dd = max; v ih = v dd v il = v ss 10 10 m a v ih1 high level input voltage 1 v dd = 3.6v v dd 0.8 v dd + 0.3 v v il1 low level input voltage 1 v dd = 3.0v 0.3 v dd 0.2 v v ih2 high level input voltage 2 v dd = 3.6v 2.4 v dd + 0.3 v v il2 low level input voltage 2 v dd = 3.0v 0.3 0.6 v v oh1 high level output voltage 3 v dd = 3.0; i oh = 4ma v dd 0.6 v v ol1 low level output voltage 3 v dd = 3.0; i ol = 4ma v ss + 0.4 v v oh2 high level output voltage 4 v dd = 3.0; i oh = 8ma v dd 0.6 v v ol2 low level output voltage 4 v dd = 3.0; i ol = 8ma v ss + 0.4 v v oh3 high level output voltage 5 v dd = 3.0; i oh = 16ma v dd 0.6 v v ol3 low level output voltage 5 v dd = 3.0; i ol = 16ma v ss + 0.4 v v oh4 high level output voltage v dd = 3.0; i oh = 24ma v dd 0.6 v v ol4 low level output voltage v dd = 3.0; i ol = 24ma v ss + 0.4 v i ihp input current (pull-down resistor) v dd = max; v in = v dd 20 120 m a notes: 1. sysvlkin 2. other inputs 3. d[31:0], /ras0, /ras1, /dcs0, /dcke, dqmh, dqml, /dreq, /dgrnt, bc32k, vdat[3:0], cp, load, df, frame, dispon, viddone, pwrcs, txd, rxd, /cs0 ~ 3, /mcs0 ~ 3, chifs, chiclk, chidout, chidin, io[6:0], spiclk, spiout, spiin, sibsync, sibout, sibmclk, sibclk, rxpwr, irout, /crad1wait, /card2wait, miox[2:0] 4. a[12:0], ale, /rd, /we /cas0 ~ 3, /cardreg, /iowr, /card1csl, /card1csh, /card2csl, /card2csh 5. dclkout
philips semiconductors preliminary specification mips PR31500 poseidon embedded processor 1996 sep 24 13 ac electrical characteristics 0.8v 2.0v delay setup hold 2.2v 0.8v 2.2v 0.8v 2.2v 0.8v outputs inputs 0.8v cc 0.2v cc sn00165 figure 3. PR31500 timing definition of ac specification
philips semiconductors preliminary specification mips PR31500 poseidon embedded processor 1996 sep 24 14 crystal oscillator characteristics 10mhz crystal sysclkin sysclkout 100 w xtal recommended 10mhz crystal nihon dempa kogyo co., ltd.: at151 c in c out sn00166 128 129 symbol parameter recommended value unit symbol parameter min. max. unit crystal oscillator f in frequency 8.25 10 mhz c i crystal impedance tbd tbd k w c in , c out external capacitors 10 33 pf 32khz crystal 79 80 c32kin c32kout xtal recommended 32khz crystal kyocera corporation: kf-38g c in c out sn00167 symbol parameter recommended value unit symbol parameter min. max. unit c in , c out external capacitors 10 33 pf
philips semiconductors preliminary specification mips PR31500 poseidon embedded processor 1996 sep 24 15 memory interface t amb = 0 to +70 c, v dd = 3.3 0.3v, external capacitance = 40pf item parameter rising/falling limits unit item parameter rising/falling min max unit 1 dclkout high time 5.4 ns 2 dclkout low time 5.4 ns 3 dclkout period 13.5 ns 4 delay dclkout to ale rising 4 ns 4 delay dclkout to ale falling 3 ns 4 delay dclkout to a[12:0] 8 ns 4 delay dclkout to d[31:16] 8 ns 4 delay dclkout to d[15:0] 1.5 8 ns 4 delay dclkout to /cs30 rising 10 ns 4 delay dclkout to /cs30 falling 10 ns 4 delay dclkout to /rd risng 8 ns 4 delay dclkout to /rd falling 7 ns 4 delay dclkout to /we rising 5 ns 4 delay dclkout to /we falling 4 ns 4 delay dclkout to /sas30 rising 1.5 ns 4 delay dclkout to /sas30 falling 1.5 ns 4 delay dclkout to /cardxcsx rising 9 ns 4 delay dclkout to /cardxcsx falling 8 ns 4 delay dclkout to /carddir rising 12 ns 4 delay dclkout to /carddir falling 11 ns 4 delay dclkout to /cardreg rising 9 ns 4 delay dclkout to /cardreg falling 10 ns 4 delay dclkout to /iord rising 10 ns 4 delay dclkout to /iord falling 9 ns 4 delay dclkout to /iowr rising 9 ns 4 delay dclkout to /iowr falling 9 ns 4 delay dclkout to /ras0 rising 6 ns 4 delay dclkout to /ras0 falling 6 ns 4 delay dclkout to /ras1 rising 1.5 8 ns 4 delay dclkout to /ras1 falling 1.5 9 ns 4 delay dclkout to dqmh/l rising 1.5 8 ns 4 delay dclkout to dqmh/l falling 1.5 9 ns 4 delay dclkout to /dcs0 rising 1.5 7 ns 4 delay dclkout to /dcs0 falling 1.5 6 ns 4 delay dclkout to dcke rising 1.5 8 ns 4 delay dclkout to dcke falling 1.5 8 ns 4 delay dclkout to /mcs30 rising 10 ns 4 delay dclkout to /mcs30 falling 10 ns 5 d[31:16] to dclkin setup time 2 ns 6 d[31:16] to dclkin hold time 1 ns 5 d[15:0] to dclkin setup time 1 ns 6 d[15:0] to dclkin hold time 1.5 ns 7 dclkout to dclkin board delay time 0 3 ns
philips semiconductors preliminary specification mips PR31500 poseidon embedded processor 1996 sep 24 16 memory interface timing diagrams 1 3 2 4 dclkout memory outputs sn00168 figure 1. memory output and clock timing 6 dclkin memory inputs 5 sn00169 figure 2. memory input timing dclkout dclkin 7 sn00170 figure 3. dclkout to dclkin
philips semiconductors preliminary specification mips PR31500 poseidon embedded processor 1996 sep 24 17 chi t amb = 0 to +70 c, v dd = 3.3 0.3v, external capacitance = 40pf item parameter rising/falling limits unit item parameter rising/falling min max unit 1 chiclk high time 100 ns 2 chiclk low time 100 ns 3 chiclk period 225 ns 4 delay chiclk rising to chidout (master) rising 5 ns 4 delay chiclk rising to chidout (master) falling 5 ns 7 delay chiclk falling to chidout (master) rising 5 ns 7 delay chiclk falling to chidout (master) falling 5 ns 4 delay chiclk rising to chifs (master) rising 5 ns 4 delay chiclk rising to chifs (master) falling 5 ns 7 delay chiclk falling to chifs (master) rising 5 ns 7 delay chiclk falling to chifs (master) falling 5 ns 4 delay chiclk rising to chidout (slave) rising 10 ns 4 delay chiclk rising to chidout (slave) falling 10 ns 7 delay chiclk falling to chidout (slave) rising 10 ns 7 delay chiclk falling to chidout (slave) falling 10 ns 4 delay chiclk rising to chifs (slave) rising 10 ns 4 delay chiclk rising to chifs (slave) falling 10 ns 7 delay chiclk falling to chifs (slave) rising 10 ns 7 delay chiclk falling to chifs (slave) falling 10 ns 5 chidin to chiclk rising setup time (master) 20 ns 6 chidin to chiclk rising hold time (master) 20 ns 8 chidin to chiclk falling setup time (master) 20 ns 9 chidin to chiclk falling hold time (master) 20 ns 5 chifs to chiclk rising setup time (slave) 20 ns 6 chifs to chiclk rising hold time (slave) 20 ns 8 chifs to chiclk falling setup time (slave) 20 ns 9 chifs to chiclk falling hold time (slave) 20 ns 5 chidin to chiclk rising setup time (slave) 20 ns 6 chidin to chiclk rising hold time (slave) 20 ns 8 chidin to chiclk falling setup time (slave) 20 ns 9 chidin to chiclk falling hold time (slave) 20 ns
philips semiconductors preliminary specification mips PR31500 poseidon embedded processor 1996 sep 24 18 chi timing diagrams 1 3 2 4 chiclk chi outputs sn00171 figure 4. chi output and clock timing (chitxedge = 1) 6 chiclk chi inputs 5 sn00172 figure 5. chi input timing (chirxedge = 1) 7 chiclk chi outputs sn00173 figure 6. chi output and clock timing (chitxedge = 0) 9 chiclk chi inputs 8 sn00174 figure 7. chi input timing (chirxedge = 0)
philips semiconductors preliminary specification mips PR31500 poseidon embedded processor 1996 sep 24 19 sib t amb = 0 to +70 c, v dd = 3.3 0.3v, external capacitance = 40pf item parameter rising/falling limits unit item parameter rising/falling min max unit 1 sibmclk high time 20 ns 2 sibmclk low time 20 ns 3 sibmclk period 50 ns 4 delay sibmclk to sibsclk rising 5 ns 5 delay sibmclk to sibsclk falling 5 ns 6 delay sibsclk rising to sibsync rising 2 ns 6 delay sibsclk rising to sibsync falling 2 ns 6 delay sibsclk rising to sibdout rising 2 ns 6 delay sibsclk rising to sibdout falling 2 ns 7 sibdin to sibsclk rising setup time 20 ns 8 sibdin to sibsclk rising hold time 0 ns sib timing diagrams 1 3 2 5 sibmclk sibsclk 4 sn00175 figure 8. sib clk timing 6 sibsclk sib outputs 8 7 sibdin sn00176 figure 9. sib timing
philips semiconductors preliminary specification mips PR31500 poseidon embedded processor 1996 sep 24 20 spi item parameter rising/falling limits unit item parameter rising/falling min max unit 1 spimclk high time 120 ns 2 spiclk low time 120 ns 3 spiclk period 250 ns 4 delay spiclk rising to spiout rising ns 4 delay spiclk rising to spiout falling ns 7 delay spiclk falling to spiout rising ns 7 delay spiclk falling to spiout falling ns 8 spiin to spiclk rising setup time 15 ns 9 spiin to spiclk rising hold time 15 ns 5 spiin to spiclk falling setup time 15 ns 6 spiin to spiclk falling hold time 15 ns spi timing diagrams 4 spiclk spiout 6 5 spiin 2 1 3 sn00177 figure 10. spi timing (phapol = 1) 7 spiclk spiout 9 8 spiin sn00178 figure 11. spi timing (phapol = 0)
philips semiconductors preliminary specification mips PR31500 poseidon embedded processor 1996 sep 24 21 video t amb = 0 to +70 c, v dd = 3.3 0.3v, external capacitance = 40pf item parameter rising/falling limits unit item parameter rising/falling min max unit 1 load pulse width 100 1600 ns 2 delay load falling to frame 100 3200 ns 3 delay load falling to df 100 3200 ns 4 delay load falling to cp 100 3200 ns 5 delay cp rising to vdat[3:0] 3 ns 6 vdat to cp rising setup 15 25 ns 7 vdat to cp rising hold 15 25 ns note: v alues shown assume a 40mhz clock for the cpu, min and max values are programmable using v ideo control registers. video timing diagrams 2 frame 1 load df 3 cp 4 5 vdat[3:0] sn00179 figure 12. video timing, 4 bit non-split lcd 7 cp vdat[3:0] 6 sn00180 figure 13. video data timing, 4 bit split lcd and 8 bit non-split lcd
philips semiconductors preliminary specification mips PR31500 poseidon embedded processor 1996 sep 24 22 power t amb = 0 to +70 c, v dd = 3.3 0.3v, external capacitance = 40pf item parameter rising/falling limits unit item parameter rising/falling min max unit 1 vstandby to /pon rising 50 ns 2 vstandby to onbutn delay time 2 s power timing diagram vstandby onbutn /pon 1 2 sn00181 figure 14. cpu reset t amb = 0 to +70 c, v dd = 3.3 0.3v, external capacitance = 40pf item parameter rising/falling limits unit item parameter rising/falling min max unit 1 /cpures low time 10 ns /cpures 1 sn00182 figure 15.
philips semiconductors preliminary specification mips PR31500 poseiden embedded processor 1996 sep 24 23 lqfp208: 208-pin plastic low profile quad flat package 28.00 0.1 156 157 105 104 208 1 53 52 0.22 0.5 1.4 (0.5) unit = mm (drawing not to scale) 1.25 typ. 1.25 typ. +0.05 0.04 0.1 0.1 29.00 0.2 0.05 0.1 0.05 1.7 max. 30.00 0.2 010 0.450.75 0.25 0.17 +0.03 0.05
philips semiconductors preliminary specification mips PR31500 poseiden embedded processor 1996 sep 24 24 philips semiconductors and philips electronics north america corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. life support applications philips semiconductors and philips electronics north america corporation products are not designed for use in life support appliances, devices, or systems where malfunction of a philips semiconductors and philips electronics north america corporation product can reasonably be expected to result in a personal injury . philips semiconductors and philips electronics north america corporation customers using or selling philips semiconductors and philips electronics north america corporation products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors and philips electronics north america corporation for any damages resulting from such improper use or sale. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 definitions data sheet identification product status definition objective specification preliminary specification product specification formative or in design preproduction product full production this data sheet contains the design target or goal specifications for product development. specifications may change in any manner without notice. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. philips semiconductors and philips electronics north america corporation register eligible circuits under the semiconductor chip protection act. ? copyright philips electronics north america corporation 1996 all rights reserved. printed in u.s.a.

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